TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 504

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

I2S0C
(180AH)
(180BH)
I2S0BUF
(1800H)
A read-
modify-
write
operation
cannot be
performed
I2S0CTL
(1808H)
(1809H)
3.18.2
bit Symbol
Read/Write
Reset State
Function
bit Symbol
Read/Write
Reset State
Function
bit Symbol
Read/Write
Reset State
Function
Bit symbol
Read/Write
Reset State
Function
bit Symbol
Read/Write
Reset State
Function
bit Symbol
Read/Write
Reset State
Function
CPU via a 32-bit data bus. The transmission buffers I2S0BUF and I2S1BUF must be
accessed using 4-byte load instructions.
SFRs
The I
0: Stop
1: Start
Source
clock
0: f
1: f
Transmission
B015
B031
2
15
31
CLKS0
S unit is provided with the following registers. These registers are connected to the
SYS
PLL
TXE0
CK07
R/W
15
15
7
0
0
7
0
B014
B030
14
30
R/W
Counter
control
0: Clear
1: Start
Figure3.18.2 I
B013
B09
*CNTE0
13
29
CK06
14
14
6
0
6
0
I2S0 Divider Value Setting Register
B012
B028
12
28
B011
B027
11
27
I2S0 Control Register
WS05
CK05
I2S0 Buffer Register
13
Divider value for CK signal (8-bit counter)
13
5
5
0
0
2
92CF26A-502
B010
Transmission buffer register (FIFO)
B026
Transmission buffer register (FIFO)
S Channel 0 Control Registers
10
26
0:MSB
1:LSB
Stereo
/monaural
0: Stereo
1: Monaural
Transmission
start bit
B009
B025
25
FSEL0
9
WS04
R/W
DIR0
CK04
12
Divider value for WS signal (6-bit counter)
12
0
0
4
4
0
0
Undefined
Undefined
B008
B024
24
8
R/W
W
W
Bit length
0: 8 bits
1: 16 bits
0: Data
1: No data
Transmission
FIFO state
B007
B023
23
TEMP0
7
WS03
CK03
BIT0
11
11
R
0
1
3
3
0
0
B006
B022
22
6
R/W
WS level
0: Low left
1: High left
Output format
00: I
01: Left 11: Reserved
DTFMT01
B005
B021
21
WLVL0
5
WS02
R/W
CK02
2
10
10
2
0
S 10: Right
0
2
0
0
B004
B020
20
4
Data output
clock edge
0: Falling
1: Rising
DTFMT00 SYSCKE0
B003
B019
19
EDGE0
3
WS01
CK01
R/W
1
9
0
0
1
9
0
0
B002
B018
18
2
System
clock
0: Disable
1: Enable
Clock
operation
(after
transmis-
sion)
0: Enable
1: Disable
B001
B017
17
TMP92CF26A
1
CLKE0
WS00
CK00
0
8
0
8
0
0
0
0
2009-06-25
B000
B016
16
0