TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 184

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

AM1
(2) Memory Access Operations After Reset
0
0
1
1
Note: The memory that is used for booting after reset must be either NOR-Flash or Masked-ROM. NAND-Flash,
determined by the AM1 and AM0 pins. The settings of the AM1 and AM0 pins and their
corresponding operation modes are as follows:
specified by the <BnBUS1:BnBUS0> bits of the control registers at any other timing.
automatically becomes effective. (The B2CSH<B2E> bit is set to 1 upon reset.).Then, the
AM1 and AM0 values that specify the data bus width are loaded into the data bus width
specification bits of the control register for the CS2 space.At the same time, the address
range ebtween 000000H and FFFFFFH is defined as the CS2 space. (The B2CSH<B2M>
is cleared to 0.)
BnCSL registers are also set up. The BnCSH<BnE> must be set to 1 to enable these
settings.
After reset, external memory is accessed using the initial data bus width that is
The values of AM1 and AM0 are effective only upon reset. The data bus width is
Upon reset, only the control registers (B2CSH and B2CSL) for the CS2 space
Then, the address spaces are configured by MSARn and MAMRn. The BnCSH and
SDRAM cannot be used.
AM0
0
1
0
1
Boots from external memory using a16-bit data bus
Boots from the on-chip boot ROM (32-bit on-chip-MROM )
92CF26A-182
Don’t use this setting
Don’t use this setting
Start Mode
(Note)
TMP92CF26A
2009-06-25