TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 73

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

3.5.1
(1) Micro DMA operation
Note: When using the micro DMA transfer end interrupt, always write “1” to bit 7 of SIMC register.
micro DMA function and HDMA function. This section explains about Micro DMA function.
For the HDMA function, please refer 3.23 DMA controller.
highest priority level for maskable interrupts (Level 6), regardless of the priority level of
the interrupt source.
placed in a stand-by state (IDLE2, IDLE1, STOP) by a HALT instruction, the requirement
of the micro DMA will be ignored (Pending).
micro DMA burst function as below.
Micro DMA processing
Micro DMA processing for interrupt requests set by micro DMA is performed at the
Because the micro DMA function is implemented through the CPU, when the CPU is
Micro DMA supports 8 channels and can be transferred continuously by specifying the
In addition to general-purpose interrupt processing, the TMP92CF26A also includes a
micro DMA /HDMA start vector register, and Micro DMA start is specified by DMA
selection register, the micro DMA triggers a micro DMA request to the CPU at
interrupt priority level 6 and starts processing the request. When IFF = 7, Micro DMA
request cannot be accepted.
interrupt at once.
channel is cleared. Data in one-byte, two-byte or four-byte blocks is automatically
transferred at once from the transfer source address to the transfer destination
address set in the control register, and the transfer counter is decremented by “1”. If
the value of the counter after it has been decremented is not “0”, DMA processing ends
with no change in the value of the micro DMA start vector register. If the value of the
decremented counter is “0”, a micro DMA transfer end interrupt (INTTC0 to INTTC7)
is sent from the CPU to the interrupt controller.
micro DMA operation is disabled and micro DMA processing terminates.
between the time at which the micro DMA /HDMA start vector is cleared and the next
setting, general-purpose interrupt processing is performed at the interrupt level set.
Therefore, if the interrupt is only being used to initiate micro DMA /HDMA (and not as
a general-purpose interrupt), the interrupt level should first be set to 0 (i.e, interrupt
requests should be disabled).
above, the level of the interrupt which is being used to initiate micro DMA processing
should first be set to a lower value than all the other interrupt levels. In this case,
edge-triggered interrupts are the only kinds of general interrupts which can be
accepted.
not based on the interrupt priority level but on the channel number: The lower the
channel number, the higher the priority (Channel 0 thus has the highest priority and
channel 7 the lowest).
When an interrupt request is generated by an interrupt source that specified by the
The 8 micro DMA channels allow micro DMA processing to be set for up to 8 types of
When micro DMA is accepted, the interrupt request flip-flop assigned to that
In addition, the micro DMA /HDMA start vector register is cleared to “0”, the next
If an interrupt request is triggered for the interrupt source in use during the interval
If micro DMA and general-purpose interrupts are being used together as described
If micro DMA requests are set simultaneously for more than one channel, priority is
92CF26A-71
TMP92CF26A
2009-06-25