TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 308

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

TB1MOD
(1192H)
A read-
modify-write
operation
cannot be
performed
Bit symbol
Read/Write
Reset State
Function
Always write “0”.
TMRB1 source clock
Control clearing for up counter (UC12)
Capture/interrupt timing
Software capture
<TB1CPM1:0>
<TB1CLK1:0>
<TB1CLE>
7
−
0
<TB1CP0I>
R/W
6
0
−
Figure 3.13.5 Register for TMRB
00
01
10
11
00
01
10
11
0
1
Software
capture
control
0: Software
capture
1:Undefined
TMRB1 Mode Register
TB1CP0I
W*
Disable
Capture to TB1CP0H/L at rising edge of TB1IN0
Capture to TB1CP0H/L at rising edge of TB1IN0
Capture to TB1CP1H/L at falling edge of TB1IN0
Capture to TB1CP0H/L at rising edge of TA3OUT
Capture to TB1CP1H/L at falling edge of TA3OUT
5
TB1IN0 pin input
φT1
φT4
φT16
Disable
Enable clearing by match with TB1RG1H/L
1
92CF26A-306
0
1
Capture timing
00:Disable
01:TB1IN0 ↑
10: TB1IN0 ↑ TB1IN0 ↓
11: TA3OUT ↑ TA3OUT ↓
TB1CPM1 TB1CPM0
INT7 occurs at
rising edge
INT7 occurs at
rising edge
INT7 occurs at
falling edge
INT7 occurs at rising
edge
The value of up counter is captured to TB1CP0H/L
Undefined
4
0
Capture control
3
0
Control
Up counter
0:Disable
1:Enable
TB1CLE
R/W
2
0
INT7 occurs at the rising
edge of TB1IN0
INT7 occurs at the rising
edge of TB1IN0
INT7 occurs at the rising
edge of TB1IN0
TMRB1 source clock
00: TB1IN0 input
01: φT1
10: φT4
11: φT16
TB1CLK1
1
0
INT7 control
TMP92CF26A
TB1CLK0
2009-06-25
0
0