TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 375

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

3.16.2.3 USBINTFRn, MRn Register
Note 1: The “INTUSB generated number” and “bit number which is set to flag register” are not always equal. In the
Note 2: Disable INTUSB (write 00H to INTEUSB register) before writing to USBINTMRn or USBINTFRn.
Mask register
Interrupt source
(Set by rising edge)
Flag register
Writing “0” to flag register
INTUSB interrupt routine, clear FLAG register (USBINTFRn) after checking it. The interrupt request flag,
which occurrs between the INTUSB interrupt routine and flag register (USBINTFRn) read, is kept in the
interrupt controller.
Therefore, after returning from the interrupt routine, the CPU jumps to INTUSB interrupt routine again.
Software support is required to avoid ending in an error routine when none of the bits in the flag register
(USBINTFRn) is set to “1”.
sources output by the UDC.
INTUSB routine, execute operations according to generated interrupt source after
checking USBINTFRn.
These SFRs control the INTUSB (only one interrupt to CPU) using the 23 interrupt
The USBINTMRn are mask registers and the USBINTFRn are flag registers. In the
The common specification for all MASK and FLAG registers is shown below.
A: The flag register is not set because mask register = “1”.
B: The flag register is not set because interrupt souce changes “1” → “0”.
C: The flag register is set because mask register = “0” and interrupt souce changes “0” → “1”.
D: The flag register is reset to “0” by writing “0” to flag register.
(
Common specifications for all mask and flag registers.)
92CF26A-373
A
B
C
D
TMP92CF26A
2009-06-25