TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 130

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

3.7.7
control register. Each bit can be set individually for input or output. Resetting sets P90 to
P92 to input port and all bits of output latch to”1”.
(1) Port 90 (TXD0), Port 91 (RXD0), Port 92 (SCLK0,
Port 9 (P90 to P92, P96, P97)
P90 to P92 are 3-bit general-purpose I/O port. I/O can be set on a bit basis using the
P96 to P97 are 2-bit general-purpose input port.
Writing “1” the corresponding bits of P9FC enables the respective functions.
Resetting resets the P9FC to “0”, and sets all bits to input ports.
pin is detailed below.
Ports 90 to 92 are general-purpose I/O port. They also function as either SIO0. Each
TXD0 output
(on bit basis)
(on bit basis)
Output latch
Direction
P9FC write
P90
P91
P92
Function
P9CR write
P9 write
P9 read
control
control
Reset
S
(Clock input or output)
(SIO0 module)
(Data output)
SIO mode
(Data input)
Figure 3.7.14 P90
SCLK0
RXD0
TXD0
A
B
Selector
Selector
92CF26A-128
S
S
A
B
UART, IrDA mode
(SIO0 module)
(Clear to send)
(Data output)
Open-drain enable
P9FC2<P90F2>
(Data input)
TXD0
RXD0
CTS
CTS )
0
0
P90 (TXD0)
TMP92CF26A
2009-06-25