TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 674

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

AC measuring condition
No. Symbol
4.3.4
1
2
3
4
5
6
7
Read
cycle
Write
cycle
t
t
t
t
t
REA
t
t
WP
NC
OH
DH
RP
DS
Note1: The “n” in “Variable” means wait-number which is set to NDFMCR0<SPLW1:0>, and “m” means number
Note2: In above variable, the setting that result is minus can not use.
NAND Flash Controller AC Characteristics
SDCLK
A0~A23
D0~D7
D0~D15
D0~D7
D0~D15
NDRE
NDWE
NDRE
NDWE
Access cycle
Read data hold time
Write data setup time
Write data hold time
which is set to NDFMCR0<SPHW1:0>.
Example: If NDFMCR0<SPLW1:0> is set to “01”, n = “1”, t
NDRE
NDRE
NDWE
low level width
data access time
low level width
Parameter
SPLW1:0 = “01”
t
t
REA
t
92CF26A-672
RP
WP
t
CYC
(1.5 + n) T − 12
(1.0 + n) T − 20
(1.0 + n) T − 20
(0.5 + m) T − 2
(2 + n + m ) T
Data output
t
DS
Min
0
Data input
Variable
RP
SPHW1:0 = “01”
= (1.5 + n) T − 12 = 2.5T − 12
(1.5 + n) T − 15
t
OH
Max
t
DH
(m=3)
(n=3)
MHz
100
80
45
41
30
30
42
0
TMP92CF26A
(m=3)
(n=3)
MHz
132
60
63
56
60
47
47
0
2009-06-25
Unit
ns