TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 28

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

3.3.3
0> to either fc, fc/2, fc/4, fc/8 or fc/16. Using the clock gear to select a lower value of f
reduces power consumption.
is necessary for the warming up time to elapse before the change occurs after writing the
register value.
is executed by the clock gear before changing. To execute the instruction following the clock
gear switching instruction by the clock gear after changing, input the dummy instruction
as follows (instruction to execute the write cycle).
internal I/O.
SYSCR1<GEAR2:0> sets the high frequency clock gear to either 1, 2, 4, 8 or 16 (fc, fc/2, fc/4,
fc/8, fc/16). These functions can reduce the power consumption of the equipment in which
the device is installed.
be PLL-OFF mode and cause the system clock (f
X2 pins.
System clock controller
(1) Clock gear controller
SYSCR1
(Example)
SYSCR1
f
(Example)
Changing clock gear
(High-speed clock gear changing)
To change the clock gear, write the register value to the SYSCR1<GEAR2:0> register. It
There is the possibility that the instruction following the clock gear changing instruction
The system clock controller generates the system clock signal (f
SYSCR0<XEN> and SYSCR0<XTEN> control enabling and disabling of each oscillator.
The combination of settings <XEN> = “1”, <SYSCK> = “0” and <GEAR2 to 0> = “100” will
For example, f
SYS
X: don't care
is set according to the contents of the Clock Gear Select Register SYSCR1<GEAR2:
EQU
LD
LD
EQU
LD
LD
Instruction to be executed after clock gear changed
SYS
10E1H
(SYSCR1),XXXXX001B
(DUMMY),00H
10E1H
(SYSCR1),XXXXX010B
(DUMMY),00H
is set to 625 kHz when the 10MHz oscillator is connected to the X1 and
92CF26A-26
;
;
;
Changes system clock f
Dummy instruction
Changes f
Dummy instruction
SYS
SYS
) to be set to fc/16 after reset.
to fc/4
SYS
to fc/2
SYS
) for the CPU core and
TMP92CF26A
2009-06-25
SYS