TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 147

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

PJ
(004CH)
PJCR
(004EH)
PJFC
(004FH)
PJDR
(0093H)
bit Symbol
Read/Write
System
Reset State
Hot Reset
State
bit Symbol
Read/Write
System
Reset State
Hot Reset
State
Function
bit Symbol
Read/Write
System
Reset State
Hot Reset
State
Function
bit Symbol
Read/Write
System
Reset State
Hot Reset
State
Function
Note: A read-modify-write operation cannot be performed for the registers PJCR and PJFC.
0: Port
1: SDCKE
PJ7D
PJ7F
PJ7
7
7
7
7
1
−
0
−
1
−
(Output latch register is
0: Port
1: NDCLE
Data from external port
PJ6C
PJ6D
0: Input, 1: Output
PJ6F
PJ6
6
6
6
6
1
−
0
−
0
−
set to “1”)
Figure 3.7.33 Register for Port J
W
−
Input/Output buffer drive register for standby mode
0: Port
1: NDALE
Port J function register
PJ5C
PJ5D
PJ5F
PJ5
Port J control register
Port J drive register
5
5
5
5
0
−
0
−
1
−
92CF26A-145
Port J register
0: Port
1:
SDLUDQM
PJ4D
PJ4F
PJ4
4
4
4
4
0
−
1
−
1
−
R/W
R/W
W
0: Port
1:
SDLLDQM
PJ3D
PJ3F
PJ3
3
3
1
−
3
3
1
−
0
−
0: Port
1:
SRWR
SDWE
PJ2D
PJ2F
PJ2
2
2
1
−
1
−
2
2
0
−
,
0: Port
1:
PJ1D
PJ1F
SRLUB
PJ1
SDCAS
1
1
−
1
1
1
−
1
0
−
,
0: Port
1:
TMP92CF26A
SRLLB
PJ0D
PJ0F
PJ0
SDRAS
0
0
1
−
0
1
−
0
0
−
2009-06-25
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