TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 132

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

P9
(0024H)
P9CR
(0026H)
P9FC
(0027H)
P9FC2
(0025H)
P9DR
(0089H)
P92 setting
<P92F>
<P92FC2>
0
1
bit Symbol
Read/Write
System
Reset State
Hot Reset
State
bit Symbol
Read/Write
System
Reset State
Hot Reset
State
Function
bit Symbol
Read/Write
System
Reset State
Hot Reset
State
Function
bit Symbol
Read/Write
System
Reset State
Hot Reset
State
Function
bit Symbol
Read/Write
System
Reset State
Hot Reset
State
Function
CTS /SCLK0
Note 1: A read-modify-write operation cannot be performed for P9CR, P9FC and P9FC2.
Note 2: When setting P96 pin to INT4 input, set P9DR<P96D> to “0” (prohibit input), and when driving P96 pin to “0”,
Don’t setting
Input port,
Input
0
0
execute HALT instruction. This setting generates INT4 inside. If don’t using external interrupt in HALT
condition, set like an interrupt don’t generated. (e.g. change port setting)
Always
write “0”
Data from external
P97D
P97
7
W
7
7
7
7
−
0
−
1
−
SCLK0 Output
Output port
port
R/W
R
−
1
0:
1: INT4
P96
port
P96D
P96F
6
W
6
6
6
−
6
0
1
−
Input
Figure 3.7.17 Register for Port 9
P91 setting
Input/Output buffer drive register for standby mode
Input
RXD0
Port 9 Function registers 2
Port 9 function register
Port 9 control register
5
Port 9 drive register
port
5
5
5
5
Input
0
92CF26A-130
Port 9 register
<P91C>
Output port
4
4
4
4
4
1
3
3
3
3
3
P90 setting
<P90F>
<P90C>
Refer to
following
table
Always
write “0”
0
1
Data from external port (Output
P92C
P92D
P92F
P92
W
W
2
2
2
0
−
−
0
−
2
1
−
0
−
2
latch register is set to “1”)
Refer to following table
Input port
setting
Don’t
0
P91C
P91D
R/W
R/W
P91
W
1
1
1
1
1
−
−
0
−
1
Output port
0:CMOS
1:Open-drain
Refer to
following
table
Output
TXD0
TMP92CF26A
P90F2
P90C
P90D
P90F
1
P90
W
W
0
0
0
0
1
−
0
0
−
0
−
0
−
2009-06-25