TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 643

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

Example 2: Mode transition to the PCM
Condition: SDRAM= Self-refresh mode
;((( Entry Self Refresh mode )))
ABP:
;((( Entry PMC mode )))
;--- PLL off setting -----
; After Wake-up
Note: SDRAMC is initialized by hot reset upon a wake-up.
The SDCKE pin output is initialized to 1 by initializing the SDRAMC. Therefore, SDRAM exits from self-refresh
mode. Auto-refresh function of the SDRAMC register is disabled at same time. Therefore, SDRAM data might
be lost.
However, though the SDRAMC is initialized by hot reset, port configurations are not initialized by Hot reset.
Thus, SDRAM can retain its contents.
To keep SDRAM data, program the PJ7 pin as the SDCKE pin and drive it low before entering the PMC mode.
The output level of the PJ7 pin while in PMC mode is determined by the PJ and PJDR register settings. Please
program the PJ7 pinto be driven low while in PMC mode in the same manner as shown above.
ld
ldw
ldw
ldw
ldw
ld
ld
ld
ei
dl
ld
ld
res
ld
ld
cp
jr
ld
nop×10
ld
ld
ld
di
ld
ld
ld
org
ld
(syscr0),40h
(wdmod),0b100h
(admod0),0000h
(admod2),0000h
(admod4),0000h
(lcdctl0),00h
(pmcctl),00h
(inte0),55h
5
0,0
(pccr),00h
(pcfc),01h
ld
(sdcmm),02h
a,(sdcmm)
a,00h
nz,ABP
(sdcmm),05h
(pj),7fh
(pjfc),1fh
(pjdr),80h
(pllcr0),00h
(pllcr1),00h
(pmcctl),80h
nop×20
046000h
(pmcctl),00h
92CF26A-641
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Enable the low-frequency clock
Disable the WDT
Disable the AD converter
Disable the LCDC
Program the warm-up time
Enable INT0 and program the interrupt level to 5
Program PC0-PC3 as INT0-INT3
Perform polling until the All Bank Precharge
Select the Self Refresh Entry command
Note: Execute at least 10 bytes of NOP or other
Disable the Self Refresh auto exit function
Select the All Bank Precharge command
Clear the PJ7 bit
Configure <PJ7> as Port function
Configure the PJDR register
Program the clock signal as: f
Stop the PLL circuit
Enable PCM condition
(Start PCM mode)
Wait until PCM is entered
Disable the PCM_ON bit
Note: At the same time, the warm-up time must
be set to default as well. (The PMCCTL register
must be written as 00H)
command is finished
instructions.
SYS
=f
OSCH
TMP92CF26A
2009-06-25