TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 447

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

DATASET = 0
Wait receiving data
DATASET = 1
(a) Single packet mode
Figure 3.16.13 is receiving sequence. Figure 3.16.14 is transmitting sequence.
This chapter focuses on access to FIFO. For Data sequence with USB host refer to
chapter 5.
can be changed between single packet and dual packet by setting EPx_SINGLE
register. Do not change packet when transferring.
Figure 3.16.13 Receiving Sequence in Single Packet Mode
This is data sequence of single packet mode when CPU bus interface is used.
Endpoint 0 cannot be changed to exclusive single packet mode. Endpoints 1 to 3
DATASET register
• Check bit of EPx_DSET_A
SIZE register
RD receiving data of size in relevant
endpoint
• Clear receiving data in FIFO
• Clear relevant bit of DATASET
• Size of SIZE_A_L confirmation
•
DATASET register
• Set bit of EPx_D SET_A
• Assert EPx_DATASET signal
Size of SIZE_A_H confirmation
register
92CF26A-445
IDLE
Receive valid data
Interrupt by EPx_FULLA
Check DATASET register
TMP92CF26A
2009-06-25