TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 23

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

X1U SB
XT1
XT2
X1
X2
3.3.1
SYSCR0<XTEN >
Oscillator circuit
Oscillator circuit
H igh frequency
Low frequency
Block diagram of system clock
φT0TMR
f
USB
f
SYS
f
φT0
OSCH
f
io
C lock Doubler0
fs
fs
× (12 or16)
Clock Doubler1
(PLL0)
(PLL1)× 24
(High/Low frequency oscillator circuit)
SYSCR0<WUEF>
SYSCR2<WUPTM1:0>
Figure 3.3.2 Block Diagram of System clock
PLLCR1<PLLON>,
PLLCR0<LUPFG>
Lock up timer
MLD/ALM
ADC
WDT
RTC
TMRA0:7,TMRB0:1
SIO0
SBI
Warming up timer
(PLL)
Prescaler
Prescaler
Prescaler
÷2
f
PLL
PLLCR0<FCSEL>
92CF26A-21
fc
÷2
÷5
fc/2
Clock gear
÷4
fc/4
f
PLLUSB
÷8
fc/8
÷16
fc/16
SYSCR0<USBCLK1:0>
SYSCR1<GEAR2:0>
Controller
SDRAMC
I/O ports
Interrupt
DMAC
USB
RAM
MAC
CPU
÷2
÷8
SYSC R0<PRCK>
NAND-Flash
Controller
Controller
÷4
Memory
LCDC
SPIC
TSI
I
2
S
÷2
÷2
TMP92CF26A
f
φT0
φT0TMR
fs
f
IO
f
SYS
f
USB
PLL
2009-06-25