TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 404

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

Request Mode
(07D9H)
bit Symbol
Read/Write
Reset State
3.16.3.20 Request Mode Register
-
Soft_Reset
G_Port_Sts
G_Config
-
Note: the TMP92CF26A doed not use this register since it does not support printer-class.
Note1: SET_ADDRESS request is supported only by auto-answer .
Note2: SET_DESCRIPTOR and SYNCH_FRAME are controlled only by software .
Note3: Vendor Request and Class Request (Printer Class and so on) are controlled only by software.
Note4: INT_SETUP, EP0, STAS and STASN interrupts assert only when it is software-control.
by control through software. Each bit represents a kind of request.
by hardware. When relevant bit in this register is set to “1”, the answer is controlled
by software. If request is received during hardware control, interrupt signal
(INT_SETUP, INT_EP0, INT_STAS, INT_STATUSN) is set to disable. If a request is
received during software control, the interrupt signal is asserted, and it is controlled
by software.
This register sets the answer for Class Request either automatically in hardware or
When relevant bit in this register is set to “0”, the answer is executed automatically
7
Soft_Reset
(Bit 7)
(Bit 6)
(Bit 5)
(Bit 4)
(Bit 3 to 0) : Reserved
R/W
6
0
G_Port_Sts
92CF26A-402
R/W
: Reserved
: SOFT_RESET
: GET_PORT_STATUS
: GET_DEVICE_ID
5
0
G_DeviceId
R/W
4
0
3
2
1
TMP92CF26A
2009-06-25
0