TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 237

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

SDLUDQM
SDLLDQM
(7) SDRAM initialization sequence
SDCKE
SDCLK
SDRAS
SDCAS
A15-A0
SDWE
SDCS
SDRAM.
commands are issued, the CPU operation (instruction fetch, execution) is halted. Before
executing the initialization sequence, appropriate port settings must be made to enable the
SDRAM control signals and address signals (A0 to A15).
to “000”.
A10
After reset release, the following sequence of commands can be executed to initialize the
The above commands are issued by setting SDCMM<SCMM2:0> to “001”. While these
After the initialization sequence is completed, SDCMM<SCMM2:0> is automatically cleared
Precharge All command
Eight Auto Refresh commands
Mode Register Set command
Precharge All
627
Auto Refresh
Figure3.10.9 Initialization Sequence Timing
Auto Refresh
92CF26A-235
227
Auto Refresh
Eight Auto Refresh commands
Auto Refresh
Auto Refresh
TMP92CF26A
2009-06-25
Mode Register
Set