TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 352

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TMP92xy26AXBG

Manufacturer Part Number
TMP92xy26AXBG
Description
Manufacturer
Toshiba
Datasheet

Specifications of TMP92xy26AXBG

Package
FPGA228
Rom Types(m=mask,p=otp, F=flash,e=eeprom)
Romless
Rom Combinations
Romless
Ram Combinations
144/288
Architecture
32-bit CISC
Usb/spi Channels
1/1
Uart/sio Channels
2
I2c/sio Bus Channels
1
(s)dram Controller
1
Adc 10-bit Channel
6
Da Converter
-
Timer 8-bit Channel
8
Timer 16-bit Channel
2
Pwm 8-bit Channels
-
Pwm 16-bit Channels
-
Cs/wait Controller
4
Dual Clock
Y
Number Of I/o Ports
136
Power Supply Voltage(v)
3.0 to 3.6
SBISR
(1243H)
A read-
modify-write
operation
cannot be
performed
Bit symbol
Read/Write
Reset State
Function
Note1: Writing in this register functions as SBICR2.
Note2: The initialdata SBISR<PIN> is “1” if SBI operation is enable (SBICR0<SBIEN>=“1”). If SBI operation is disable
(SBICR0<SBIEN>=“0”), the initialdata of SBISR<PIN> is “0”.
Master/ Slave
status
monitor
0:Slave
1:Master
MST
7
0
Transmitter/
Receiver
status
monitor
0:Receiver
1:Tranmitter
Figure 3.15.6 Registers for the I
TRX
6
0
Serial Bus Interface Status Register
I
monitor
0:Free
1:Busy
2
C bus status
BB
5
0
92CF26A-350
INTSBI
interrupt
request
monitor
0: Interrupt
1: Interrupt
requested
canceled
PIN
4
1
R
Arbitration
lost detection
monitor
0: −
1: Detected
2
C bus mode
AL
3
0
Last received bit monitor
GENERAL CALL detection monitor
Slave address match detection monitor
Arbitration lost detection monitor
0
1
0
1
0
1
0
1
Slave
address
match
detection
monitor
0:Undetected
1: Detected
Slave address don’t match or Undetected
Slave address match or GENERAL CALL
detected
AAS
Last received bit was 0
Last received bit was 1
Undetected
GENERAL CALL detected
Arbitration lost
2
0
GENERAL
CALL
detection
monitor
0:Undetected
1: Detected
AD0
1
0
TMP92CF26A
Last
received bit
monitor
0: 0
1: 1
2009-06-25
LRB
0
0

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