TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 347

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TMP92xy26AXBG

Manufacturer Part Number
TMP92xy26AXBG
Description
Manufacturer
Toshiba
Datasheet

Specifications of TMP92xy26AXBG

Package
FPGA228
Rom Types(m=mask,p=otp, F=flash,e=eeprom)
Romless
Rom Combinations
Romless
Ram Combinations
144/288
Architecture
32-bit CISC
Usb/spi Channels
1/1
Uart/sio Channels
2
I2c/sio Bus Channels
1
(s)dram Controller
1
Adc 10-bit Channel
6
Da Converter
-
Timer 8-bit Channel
8
Timer 16-bit Channel
2
Pwm 8-bit Channels
-
Pwm 16-bit Channels
-
Cs/wait Controller
4
Dual Clock
Y
Number Of I/o Ports
136
Power Supply Voltage(v)
3.0 to 3.6
3.15 Serial Bus Interface (SBI)
I
2
canceller
C bus mode
3.15.1
Noise
f
SYS
/4
supports only I
in the I
Each pin is specified as follows.
The TMP92CF26A has a 1-channel serial bus interface which an I
The serial bus interface is connected to an external device through PV6 (SDA) and PV7 (SCL)
Configuration
SBI control
SBI status
SBICR2/
register 2/
Divider
I
sync. +
control
control
SBISR
register
2
clock
clock
2
C bus
SIO
C bus mode.
PVFC2<PV7F2, PV6F2>
2
C bus mode (Multi master).
Transfer
address
register
I
control
I2CAR
2
circuit
C bus
Figure 3.15.1 Serial bus interface (SBI)
11
INTSBI interrupt request
SBI data
SBIDBR
register
register
buffer
Shift
92CF26A-345
PVCR<PV7C, PV6C>
register 0, 1
SBI control
SBICR0, 1
data control
data control
I
2
C bus
SIO
11
SBI baud rate
canceller
SBIBR0
register 0
Noise
2
PVFC<PV7F, PV6F>
C bus mode. This circuit
SCL
SCK
SO
SI
SDA
control
output
Input/
11
TMP92CF26A
2009-06-25
PV6
(SDA)
PV7
(SCL)

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