TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 216

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

LOCALESX
(08A0H)
(08A1H)
3.9.2.5
Bit Symbol
Read/Write
Reset State
Function
Bit Symbol
Read/Write
Reset State
Function
the high-speed data transfer by enabling the internal DMAC to become the bus master.
(Please refer to Section 3.6, “DMA Controller”.)
registers for the CPU and LCDC. Regardless of the settings of the bank registers for
program, read and write data of the CPU, the banks to be used as source address memory
and destination address memory are specified individually during DMA operations.
performed by dividing those channels into 2 groups. The DMA channels with the
even-channel number, 0, 2 and 4, are classified into the E-group (ES and ED groups); while
the channels with the odd-channel number, 1 and 3, are classified into the O-group (OS and
OD groups). These registers cannot specify bank numbers for each channel, but specifies
one bank number for all the channels in the same group.
the LOCAL-X area, and also specify bank 2 for storing DMA-destination addresses in the
LOCAL-Y area. If the DMA operation for channel 0 is initiated Assume that the source and
destination addresses specified by the DMA operation, which is described in Section 3.6,
are set into the LOCAL-X and LOCAL-Y areas, respectively. Then, if the DMA operation
for channel 0 is initiated, bank 1 in the LOCAL-X area is configured as the source address
memory, and bank 2 in the LOCAL-Y area is configured as the destination address memory.
(Example)
The TMP92CF26A supports not only the read and write operations of the CPU, but also
These registers are provided specially for the DMA operation, separately from the bank
The DMAC of the TMP92CF26A supports six channels, and the bank control is
The following example shows how to specify bank 1 for storing DMA-source addresses in
DMA-Function Bank Registers
Bank for
LOCAL-X
0: Disable
1: Enable
DMA operation for channel 0 is started
R/W
LXE
15
X7
7
0
0
ldw
ldw
(Since bank 0 is overlapping with the COMMON area, this filed must not be specified as 0.)
LOCAL-X Register for the E-group DMA Source
(localesx), 8001h
(localedy), 8002h
14
X6
6
0
Settings of the X8 through X0 bits and their corresponding chip select signals
Specify the bank number for the LOCAL-X area
13
92CF26A-214
X5
5
0
Specify the bank number for the LOCAL-X area
000000000 to 011111111 CSXA
100000000 to 111111111 CSXB
12
;
;
X4
4
0
Specify DMA-source bank number for channel 0
Specify DMA-destination bank number for channel 0
R/W
X3
11
3
0
10
X2
2
0
X1
1
9
0
TMP92CF26A
2009-06-25
R/W
X0
X8
0
8
0
0