TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 523

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

LCDO0DLY
(0291H)
LCDHSDLY
(028FH)
LCDLDDLY
(0290H)
LCDO1DLY
(0292H)
LCDO2DLY
(0293H)
bit Symbol
Read/Write
Reset State
Function
bit Symbol
Read/Write
Reset State
Function
bit Symbol
Read/Write
Reset State
Function
bit Symbol
Read/Write
Reset State
Function
bit Symbol
Read/Write
Reset State
Function
Data output
0: Sync with
1: 1 clock
timing
LLOAD
later than
LLOAD
PDT
R/W
7
7
7
7
7
0
OE0D6
OE1D6
OE2D6
HSD6
LDD6
6
6
0
6
6
6
0
0
0
0
LHSYNC Delay Register
LLOAD Delay Register
LGOE0 Delay Register
LGOE1 Delay Register
LGOE2 Delay Register
92CF26A-521
OE0D5
OE1D5
OE2D5
HSD5
LDD5
5
5
5
5
5
0
0
0
0
0
OE0D4
OE1D4
OE2D4
HSD4
LDD4
4
0
4
4
0
4
0
4
0
0
LHSYNC delay (bits 6-0)
LLOAD delay (bits 6-0)
OE0 delay (bits 6-0)
OE1 delay (bits 6-0)
OE2 delay (bits 6-0)
OE0D3
OE1D3
OE2D3
HSD3
LDD3
W
W
W
W
W
3
3
3
3
0
3
0
0
0
0
OE0D2
OE1D2
OE2D2
HSD2
LDD2
2
2
2
2
2
0
0
0
0
0
OE0D1
OE1D1
OE2D1
HSD1
LDD1
1
0
1
1
0
1
0
1
0
0
TMP92CF26A
2009-06-25
OE0D0
OE1D0
OE2D0
HSD0
LDD0
0
0
0
0
0
0
0
0
0
0