TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 315

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

Timer output pin TB0OUT0
Count clock
(Prescaler output clock)
TB0IN0 pin input
(External trigger pulse)
Match with TB0RG0H/L
Match with TB0RG1H/L
(4) Application examples of capture function
1.
2.
3.
1.
Used capture function, they can be applied in many ways, for example;
input the external trigger pulse from TB0IN0 pin, and load the value of up
counter into capture register TB0CP0H/L at the rising edge of the TB0IN0 pin.
the TB0CP0H/L value (c) plus a delay time (d) to TB0RG0H/L (=c+d), and set the
above set value (c+d) plus a one-shot pulse width (p) to TB0RG1H/L (=c+d+p).
TB0FF0 inversion is enabled only when the up counter value matches
TB0RG0H/L or TB0RG1H/L. When interrupt INTTB01 occurs, this inversion will
be disabled after one-shot pulse is output.
One-shot pulse output from external trigger pulse
Frequency measurement
Pulse width measurement
One-shot pulse output from external trigger pulse
Set the up counter UC10 in free-running mode with the internal input clock,
When the interrupt INT6 is generated at the rising edge of TB0IN0 input, set
The TB0FFCR<TB0E1T1, TB0E0T1> register should be set “11” and that the
The (c), (d) and (p) correspond to c, d, and p in the Figure 3.13.12.
Figure 3.13.12 One-shot Pulse Output (with delay)
c
Set the counter in free-running mode.
Disable inversion
caused by loading into
TB0CP0H/L
Load to capture registesr 0 (TB0CP0H/L)
INT6 occured
92CF26A-313
Delay time
Inversion
enable
(d)
c + d
Inversion
enable
Pulse width
(p)
c + d + p
INTTB01 occured
TMP92CF26A
2009-06-25