TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 104

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

Sample2: Calculation examples for CPU + LDMA
Conditions 1:
Calculation example 1:
Conditions 2:
Calculation example 2:
CPU operation speed (f
Display RAM
Display size
Display quality
Refresh rate
t
LHSYNC [period: s]
CPU bus stop rate
CPU operation speed (f
Display RAM
Display size
Display quality : 4096 colors (STN)
Refresh rate
t
LHSYNC [period: s]
CPU bus stop rate
STOP
STOP
(LDMA)
(LDMA)
: 16-bit external SRAM (0 waits)
: QVGA (240seg × 320com)
: 100 Hz (0 dummy cycles)
SYS
SYS
92CF26A-102
: Internal RAM
: QVGA (320seg × 240com)
: 65536 colors (TFT)
: 70 Hz (including 20 clocks of dummy cycles)
= ((SegNum × K / 8) × t
= 1/70 [Hz] / (COM+20=260) = 54.95 [μs]
= t
= (SegNum × K / 8) × t
= 1/100 [Hz] / (COM = 240) = 41.67 [μs]
= t
)
)
STOP
STOP
(LCD)[s] / LHSYNC [period: s]
(LCD)[s] / LHSYNC [period: s]
: 60 MHz
= ((320 × 16 / 8) × 1 / f
= ((640) × 16.67 [ns] / 4) + 16.67 [ns]
= 2.68 [μs]
= 2.68 [μs] / 54.95 [μs] = 4.88 [%]
: 10 MHz
= (240 × 12 / 8) × (2 + wait count) / f
= (360) × 200 [ns] / 2
= 36 [μs]
= 36 [μs] / 41.67 [μs] = 86.40 [%]
LRD
LRD
) + (1 / f
SYS
SYS
[Hz] / 4) + (1 / f
[Hz])
TMP92CF26A
SYS
2009-06-25
[Hz] / 2
SYS
[Hz])