TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 402

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

EOP
(07CFH)
bit Symbol
Read/Write
Reset State
3.16.3.17 EOP Register
Note1: EOP<EP7_EOPB, EP6_EOPB, EP5_EOPB, EP4_EOPB> registers are not used in the TMP92CF26A.
Note2: When writing to this register, a recovery time of 5clocks at 12MHz is needed. After writing this register, insert
dummy instruction of 420 ns or longer.
short packet is transmitting bulk-IN or interrupt-IN.
transmission data is written to the FIFO, or read all receiving data from the FIFO.
The UDC terminates its status stage on this signal.
this to terminate writing of transmission data. In this case, write “0” to <EP0_EOPB>
of writing endpoint. Write “1” to other bits.
This register is used when a control transfer type dataphase terminates or when a
In a control transfer type dataphase, write “0” to <EP0_EOPB> when all
When a short packet is transmitted by using bulk-IN or interrupt-IN endpoint, use
EP7_EOPB
W
7
1
EP6_EOPB
W
6
1
EP5_EOPB
92CF26A-400
W
5
1
EP4_EOPB
W
4
1
EP3_EOPB
W
3
1
EP2_EOPB
W
2
1
EP1_EOPB
W
1
1
TMP92CF26A
2009-06-25
EP0_EOPB
W
0
1