TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 485

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

Note: The SD card of the TMP92CF26A supports a baud rate of up to 20 Mbps. This field should be programmed so
(h) SWRST
(i) XEN
(j) CLKSEL2:0
that SPCLK signal does not exceed 20 MHz When setting the baud rates, select less than 20 Mbps according
to the operation speed of CPU (f
transmission and reception. Stop the data transmission after writing a 0 to the
SPICT<TXE> bit where XEN = 1. Then, write a 1 to the SWRST bit to initialize the
read and write pointers of transmit and receive FIFO buffers.
UNIT data that is currently being transmitted. Then, writing a 1 to the SWRST bit
invalidate the data in the transmit FIFO buffer. Therefore, the data is not output even
if the data transmission is restarted after performing a software reset.Do not write a 1
to the SWRST bit in the middle of data transmission.
buffer becomes invalid.
even if the data in the receive FIFO buffer becomes invalid. Therefore, stop data
reception by writing a 0 to the SPICT<RXE> bit after receiving the data that is
currently being received. Then, (after confirming there is no UNIT data currently
being received, or ) the receive operation can be stopped completely by writing a 1 to
the SWRST bit after checking no UNIT data in receiving (namely after REND
interrupt or the time to receive 1UNIT).
performed in a single-shot operation, which is to write a 1 to the SWRST bit (it is not
required to write a 0 to the SWRST bit). Simultaneous writing of 1s to the XEN and
SWRST bits is also supported.
using the SPI controller.
and is programmable as shown below according to the system clock settings.
these bits
This bit is used to performs a software reset of the read and write pointers for data
Writing a 0 to the SPICT<TXE> bit stops data transmission after transmitting the
In case of performing data reception, the received data contained in the receive FIFO
However, when performingSequential-mode data reception, data reception continues
This bit enables or disables the internal clock signal. Always set this bit to 1 when
This bti selects the baud rate. The baud rate is generated using the system clock f
Data transmission or reception must not be performed while changing the state of
Do not write a 1 to the SWRST bit during a data reception. Software reset can be
<CLKSEL2:0>
f
f
f
SYS
f
f
f
SYS
SYS
f
SYS
SYS
SYS
SYS
/256
Table 3.17.1 Example of Baud Rate
/16
/64
/2
/3
/4
/8
SYS
92CF26A-483
).
f SYS = 60 MHz
0.234375
0.9375
3.75
7.5
20
15
−
Baud Rate [Mbps]
f SYS = 80 MHz
0.3125
1.25
20
10
−
−
5
TMP92CF26A
2009-06-25
SYS