TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 157

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

3.7.17
input or output. Resetting sets port P1 to P5 to input port and output latch to “0”.
output pin for timers (TA3OUT, TA5OUT, TA7OUT), as an input pin for timers (TB0IN0,
TB1IN0), and as an input pin for external interruption (INT5 to INT7).
pin for timers (TB0OUT0, TB1OUT1).
interruption controller.
INT7 don’t depend on IIMC1 register setting.
TBnMOD<TBnCPM1:0>.
Port P (PP1 to PP7)
Ports P1 to P5 are 6-bit general-purpose I/O ports. Each bit can be set individually for
In addition to functioning as general-purpose I/O port, P0 to P5 can also function as an
Port P6 and P7 are 2-bit output port. Resetting sets output latch to “0”.
In addition to functioning as an output port, PP6 and PP7 can also function as an output
Setting in the corresponding bits of PPCR and PPFC enables the respective functions.
The edge select for external interruption is determined by the IIMC register in the
In port setting, if 16 bit timer input is selected and capture control is executed, INT6 and
TA3OUT output
TA5OUT output
(on bit basis)
(on bit basis)
Output latch
PPCR write
PPFC write
Direction
Function
PP write
PP read
control
control
Reset
R
Figure 3.7.44 Port P1, P2
A
B
Selector
Selector
92CF26A-155
S
S
A
B
INT6 and INT7 operate by setting
PP1 (TA3OUT)
PP2 (TA5OUT)
TMP92CF26A
2009-06-25