TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 589

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

3.20.6
1. Debounce circuit
2. Port setting
Use Cautions
supplied to the CPU (during IDLE1 and STOP modes, or PCM state), the debounce
circuit does not operate. Because of this, interrupts bypassing the debounce circuit
are not generated either.
and STOP modes, or the PCM state, set the debounce circuit to disable before
entering the HALT or PCM state. (TSICR1<DBC7>= “0”)
the intermediate voltage is also applied to the normal C-MOS input gates (P96 and
P97) due to the circuit structure.
TSICR0<INGE>. At this time (TSICR0<INGE>= “1”). Note that blocking the input
to the C-MOS logics sets “1” at all times in TSICR0<PTST> that confirms a first
pen-touch.
The CPU system clock is used in debounce circuit. Therefore, when no clock is
When using a startup that uses the TSI starting from the state during IDLE1
When an intermediate voltage of 0 V to AVcc is converted using the AD converter,
Take measures against the flow-through current to Port 96 and 97 by using
92CF26A-587
TMP92CF26A
2009-06-25