TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 370

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

3.16.1.1 System Configuration
PWM
DPLL
SIE
Descriptor RAM
The USB controller (UDC) consists of the following 3 blocks.
1.
2.
3.
384 bytes
UDC core
900/H1 CPU I/F (details given in Section 3.16.2, below).
UDC core block (DPLL, SIE, IFM and PWM), request controller, descriptor
RAM and 4 endpoint FIFO (details given in Section 3.16.3, below).
USB transceiver
IFM
I/F
manager
FIFO
Figure 3.16.1 UDC Block Diagram
92CF26A-368
Request controller
UDC
FIFO (64 bytes × 1)
FIFO (64 bytes × 2)
FIFO (64 bytes × 2)
FIFO (8 bytes × 1)
Endpoint 0:
Endpoint 1:
Endpoint 2:
Endpoint 3:
900/H1 CPU
interface
transceiver
USB
TMP92CF26A
2009-06-25
ADDRESS
WR
RD
D+
D−