TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 124

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

P6FC
(001BH)
P6DR
(0086H)
P6
(0018H)
P6CR
(001AH)
bit Symbol
Read/Write
System
Reset State
Hot Reset
State
bit Symbol
Read/Write
System
Reset State
Hot Reset
State
Function
bit Symbol
Read/Write
System
Reset State
(Note2)
Hot Reset
State
Function
bit Symbol
Read/Write
System
Reset State
Hot Reset
State
Function
Note1: A read-modify-write operation cannot be performed for P6CR, P6FC.
Note2: It is set to “Port” or “Data bus” by AM pins state.
P67C
P67F
P67D
P67
0/1
−
7
7
7
7
1
0
−
−
P66C
P66D
P66F
P66
0/1
−
6
6
6
6
1
0
−
−
Data from external port (Output latch register is cleared to “0”)
Figure 3.7.8 Register for Port 6
Input/Output buffer drive register for standby mode
Port 6 Drive buffer register
Port 6 Function register
Port 6 Control register
P65C
P65F
P65D
P65
0/1
0
−
5
5
5
−
5
1
−
92CF26A-122
0: Port 1:Address bus (A16 to A23)
Port 6 register
P64C
P64F
P64D
P64
0:Input 1:Output
0/1
4
4
0
−
4
−
4
−
1
R/W
R/W
W
W
−
P63C
P63F
P63D
P63
0/1
3
3
3
−
−
3
−
0
1
P62C
P62F
P62D
P62
0/1
2
2
2
−
−
2
0
1
−
P61C
P61F
P61D
P61
0/1
1
1
1
−
0
−
1
−
1
TMP92CF26A
P60C
P60D
P60F
P60
0/1
0
0
0
0
−
−
0
1
−
2009-06-25