TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 514

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

3.18.4
(Example settings) I2S0WS = 8 kHz, I2SnCKO = 400 kHz, data transmission on the rising edge (at f
(Main routine)
INTEI2S01
I2S0CTL
(INTI2S Interrupt Routine)
X: Don't care, −:  N o change
PFCR
PFFC
I2S0C
I2S0CTL
I2S0BUF
I2S0BUF
Figure3.18.5 Connection Example between the TMP92CF26A and an External LSI
Note: After reset, PF0 to PF2 are placed in a high-impedance state. Connect each pin with a pull-up or pull-down
Detailed Description of Operation
(1) Connection example
(2) Operation procedure
resistor as necessary.
external LSI (DA converter) using channel 0.
units. Whenever each 64-byte buffer space becomes empty, an INTI2Sn interrupt is
generated. The next data to be transmitted should be written to the FIFO in the
interrupt routine.
Figure3.18.5 shows an example of connections between the TMP92CF26A and an
The I
Example settings and timing diagram are shown below.
2
S unit incorporates a 128-byte FIFO buffer that is divided into two 64-byte
X
X
X
TMP92CF26A
7
−
1
0
0
1
0
*
*
*
*
*
*
*
*
(Transmit)
PF2/I2S0WS
PF0/I2SCKO
X
X
0
X
0
X
X
6
−
1
*
*
*
*
*
*
*
*
PF1/I2SDO
X
X
X
X
5
−
−
−
0
1
*
*
*
*
*
*
*
*
X
4
−
−
−
1
1
0
0
0
*
*
*
*
*
*
*
*
X
X
X
3
−
−
0
0
1
1
*
*
*
*
*
*
*
*
2
0
−
1
1
0
0
0
0
0
*
*
*
*
*
*
*
*
92CF26A-512
1
0
−
1
1
1
0
0
0
0
*
*
*
*
*
*
*
*
0
1
−
1
0
0
1
0
1
0
*
*
*
*
*
*
*
*
WS
CK
DATA
Example: DA converter
(Receive)
Set interrupt level.
Set pins: PF0 (I2S0CKO), PF1 (I2S0DO), PF2 (I2S0WS)
Divider value N=150
Divider value K=50
Set transmit mode (I
Falling edge, WS=0 Left, clock stop.
Write left and right data to FIFO (4 bytes × 32 = 128 bytes).
Start transmission.
Write left and right data to FIFO (4 bytes × 16 = 64 bytes).
2
S mode, MSB-first, 16-bit).
SYS
TMP92CF26A
= 50 MHz)
2009-06-25