TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 222

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

address
400000H
4000xxH
5000yyH
Logical
•
•
•
•
•
•
•
(b) Subroutine (Bank 0 in LOCAL-Y)
The instructions No.17 and No.18 configure bank 1 of the LOCAL-Y area. In this case, the
The instruction No.19 configures Bank 0 of the LOCAL-Z area to read data from
The instructions No.20 and No.21 are used to read data from character-ROM. When the
The instruction No.23switches the program bank in the LOCAL area. Since the program
The instructions No.24 and No.25 are used to write data to SRAM. When the CPU
The instruction No.30 starts LCD display operation.
CPU writes the LCD Display data to Display RAM, and the data is then read by the
LCDC. Thus, the LOCALWY and LOCALLY registers should be programmed to specify
the same bank, bank1.
character-ROM.
CPU generates the address 800000H, the MMU translates it to the physical address
000000H, which is then placed onto the external address bus: A23 to A0. Since the logical
address is within the address range of the CS2 space,
the same time. By using these instructions, the CPU can read data from character ROM.
bank switching within the same LOCAL area is prohibited, this is a bad example.
generates the address 400000H, the MMU translates it to the physical address 200000H,
which is then placed onto the external address bus: A23 to A0. Since the logical address is
within the address range of the CS1 space,
using these instructions, the CPU can write data to SRAM.
When the LCDC generates the address 400000H in a DMA cycle, the MMU translates it
to the physical address 200000H, which is then placed onto the external address bus: A23
to A0. Since the logical address is within the address range of the CS1 space,
SRAM is asserted at the same time. By using these instructions, the LCDC can read data
from SRAM.
The instructions No.28 and No.29 load the LCD starting address into the LCD Controller.
Physical
address
0000xxH
000000H
1000yyH
Instruction
No.
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
org
ldw
ldw
ldw
ld
ld
ld
ld
ld
ld
ld
ld
ret
:
:
:
:
92CF26A-220
(localpy), 82H
(xix), bc
(lsarcl), xiz
(lcdctl0),01H
400000H
xiy,800000H
wa,(xiy)
xix, 400000H
xiz, 400000H
(locally), 8001H
(localwy),8001H
(localrz), 8001H
Instruction
CS
1
for SRAM is asserted at the same time. By
;
; Bank 1 in LOCAL-Y is configured as
; Bank 1 in LOCAL-Y is configured as LCD
; Bank 0 in LOCAL-Z is configured as
; Index address register for reading
; Read Character-ROM
; Convert the read data to display-data
;
; Index address register for writing LCD
; Write LCD Display data
; Configure the LCD Controller
;
; Load the LCD Start address into LCDC
;
; Start LCD Display operation
;
;
write-data memory for LCD Display RAM
display RAM
read-data memory for Character-RAM
Character-ROM
Display data
CSZA
for NOR-Flash is asserted at
Comment
TMP92CF26A
2009-06-25
CS
1
for