TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 663

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

Note1: The phase relation between X1 input signal and the other signals is undefined.
Note2: The above timing chart show an example of basic bus timing. The
D0~D15
A0~A23
SDCLK
SRWR
SRxxB
pins timing can be adjusted by memory controller timing adjust function.
WAIT
(1) Read cycle (0 waits)
R/
CSn
RD
X1
W
t
RRH
t
t
AR
CL
t
OSC
t
CYC
92CF26A-661
t
t
t
RK
CH
AD
t
SBA
t
TK
t
KT
t
t
RR
RD
CSn
, R/ W ,
Data input
RD
,
WRxx
t
t
HA
HR
,
TMP92CF26A
SRxxB
2009-06-25
,
SRWR