TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 135

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

3.7.9
or output. Resetting sets Port C to an input port. It also sets all bits of the output latch
register to “1”.
input pin for timers (TA0IN, TA2IN), input pin for external interruption (INT0 to INT3),
Extension address function (EA26, EA27, EA28) and output pin for Key (KO8). These
settings are mode using the function register PCFC. The edge select for external
interruption is determined by the IIMC register in the interruption controller.
(1) PC0 (INT0), PC2 (INT2)
Port C (PC0 to PC7)
PC0 to PC7 are 8-bit general-purpose I/O port. Each bit can be set individually for input
In addition to functioning as a general-purpose I/O port, Port C can also function as an
Direction control
Function control
Output latch
PCCR write
PC read
PCFC write
INT0
INT2
PCwrite
Reset
S
Figure 3.7.20 Port C0, C2
92CF26A-133
Selector
Rising/Falling selection
IIMC<I0LE, I0EDGE>
Level/edge selection
S
<I2LE, I2EDGE>
B
A
and
PC0 (INT0)
PC2(INT2)
TMP92CF26A
2009-06-25