CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 98
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CP80617004119AES LBU3
Manufacturer Part Number
CP80617004119AES LBU3
Description
Manufacturer
Intel
Datasheet
1.CP80617004119AES_LBU3.pdf
(388 pages)
Specifications of CP80617004119AES LBU3
Lead Free Status / RoHS Status
Compliant
- Current page: 98 of 388
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1.9.18
98
C0DTPEW - Channel 0 DRAM Rank Throttling Passive Event
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
Programmable Event weights are input into the averaging filter. Each Event weight is an
normalized 8-bit value that the BIOS must program. The BIOS must account for burst
length and 1N/2N rule considerations. It is also possible for BIOS to take into account
loading variations of memory caused as a function of memory types and population of
ranks. GMCH implements 4 independent filters, one per rank. All bits in this register
can be locked by the DTLOCK bit in the C0DTC register.
31:24
23:16
15:8
7:0
Bit
Access
RW-L
RW-L
RW-L
RW-L
Default
Value
00h
00h
00h
00h
Reserved
Reserved
Reserved
Reserved
0/0/0/MCHBAR
2A8-2ABh
00000000h
32 bits
RW-L
Description
Processor Configuration Registers
Datasheet
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