CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 278

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

1.18.14
278
PMEM_REG - Protected Memory Enable Register
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
Register to enable the DMA protected memory regions setup through the PLMBASE,
PLMLIMT, PHMBASE, PHMLIMIT registers. When LT.CMD.LOCK.PMRC command is
invoked, this register is locked (treated RO). When LT.CMD.UNLOCK.PMRC command is
invoked, this register is unlocked (treated RW). This register is always treated as RO
(0) for implementations not supporting protected memory regions (PLMR and PHMR
fields reported as 0 in the Capability register).
30:1
Bit
31
Access
RW
RO
0000000
Default
Value
0h
0h
Enable Protected Memory (EPM)
This field controls DMA accesses to the protected low-memory
and protected high-memory regions.
0 = DMA accesses to protected memory regions are handled as
1 = DMA accesses to protected memory regions are handled as
Software must not depend on hardware protection of the
protected memory regions, and must ensure the DMA-
remapping structures are properly programmed to not allow
DMA to the protected memory regions. Hardware reports the
status of the protected memory enable/
disable operation through the PRS field in this register.
Hardware implementations supporting DMA draining must
drain any in-flight translated DMA requests queued within the
root complex before indicating the protected memory region as
enabled through the PRS field.
Reserved
• If DMA-remapping hardware is not enabled, DMA requests
• If DMA-remapping hardware is enabled, DMA requests are
• If DMA-remapping hardware is not enabled, DMA to
• If DMA-remapping hardware is enabled, hardware may or
(including those to protected regions) are not blocked.
translated per the programming of the DMA-remapping
structures. Software may program the DMA-remapping
structures to allow or block DMA to the protected memory
regions.
protected memory regions are blocked. These DMA
requests are not recorded or reported as DMA-remapping
faults.
may not block DMA to the protected memory region(s).
follows:
follows:
0/0/0/VC0PREMAP
64-67h
00000000h
RO; RW
32 bits
(Sheet 1 of 2)
Description
Processor Configuration Registers
Datasheet