CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 308

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

1.19.4
308
GCMD_REG - Global Command Register
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
Register to control DMA-remapping hardware. If multiple control fields in this register
need to be modified, software must serialize the modifications through multiple writes
to this register.
Bit
Bit
31
0
Access
Access
RO
W
Default
Default
Value
Value
0b
0b
Translation Enable (TE)
Software writes to this field to request hardware to enable/
disable DMA-remapping hardware.
0 = Disable DMA-remapping
1 = Enable DMA-remapping
Hardware reports the status of the translation enable
operation through the TES field in the Global Status register.
There may be active DMA requests in the platform when
software updates this field. Hardware must enable or disable
remapping logic only at deterministic transaction boundaries,
so that any in-flight transaction is either subject to
remapping or not at all.
Hardware implementations supporting DMA draining must
drain any in-flight DMA read/write requests queued within
the root complex before completing the translation enable
command and reflecting the status of the command through
the TES field in the GSTS_REG.
Value returned on read of this field is undefined.
Coherency (C)
This field indicates if hardware access to the root, context,
page-table and interrupt remap structures are coherent
(snooped) or not.
0 = Indicates hardware accesses to remapping structures
1 = Indicates hardware accesses to remapping structures
Hardware access to advanced fault log and invalidation
queue are always coherent.
0/0/0/DMIVC1REMAP
18-1Bh
00000000h
32 bits
are incoherent.
are coherent.
RO; W
(Sheet 1 of 5)
(Sheet 3 of 3)
Processor Configuration Registers
Description
Description
Datasheet