CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 157

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

Processor Configuration Registers
1.13.6
1.13.7
Datasheet
CC1 - Class Code
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
This register identifies the basic function of the device, a more specific sub-class, and a
register- specific programming interface.
CL1 - Cache Line Size
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
23:16
15:8
7:0
Bit
7:0
Bit
Access
Access
RW
RO
RO
RO
Default
Default
Value
Value
00h
06h
04h
00h
Cache Line Size (Scratch pad)
Implemented by PCI Express devices as a read-write field for
legacy compatibility purposes but has no impact on any PCI
Express device functionality.
Base Class Code (BCC)
Indicates the base class code for this device. This code has
the value 06h, indicating a Bridge device.
Sub-Class Code (SUBCC)
Indicates the sub-class code for this device. The code is 04h
indicating a PCI to PCI Bridge.
Programming Interface (PI)
Indicates the programming interface of this device. This
value does not specify a particular register set layout and
provides no practical use for this device.
0/1/0/PCI
9-Bh
060400h
RO
24 bits
0/1/0/PCI
Ch
00h
RW
8 bits
Description
Description
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