CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 257

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

Processor Configuration Registers
Datasheet
12:8
Bit
7
6
5
Access
RO
RO
RO
RO
Default
00010b
Value
0b
1b
1b
Supported Adjusted Guest Address Widths (SAGAW)
This 5-bit field indicates the supported adjusted guest address
widths (which in turn represents the levels of page-table
walks) supported by the hardware implementation. A value of
1 in any of these bits indicates the corresponding adjusted
guest address width is supported. The adjusted guest address
widths corresponding to various bit positions within this field
are:
0: 30-bit AGAW (2-level page table)
1: 39-bit AGAW (3-level page table)
2: 48-bit AGAW (4-level page table)
3: 57-bit AGAW (5-level page table)
4: 64-bit AGAW (6-level page table)
Software must ensure that the adjusted guest address width
used to setup the page tables is one of the supported guest
address widths reported in this field.
Caching Mode (CM)
0 = Hardware does not cache not present and erroneous
1 = Hardware may cache not present and erroneous
Refer to Section 8.4.9 for more details on caching mode.
Hardware implementations are recommended to support
operation corresponding to CM=0.
Protected High-Memory Region (PHMR)
0 = Indicates protected high-memory region not supported.
1 = Indicates protected high-memory region is supported.
DMA-remapping hardware implementations on Intel VT-d
platforms supporting main memory above 4 GB are required
to support protected high-memory region.
Protected Low-Memory Region (PLMR)
0 = Indicates protected low-memory region not supported.
1 = Indicates protected low-memory region is supported.
DMA-remapping hardware implementations on Intel TXT
platforms are required to support protected low-memory
region.
entries in the context-cache and IOTLB. Invalidations are
not required for modifications to individual not present or
invalid entries. However, any modifications that result in
decreasing the effective permissions or partial permission
increases require invalidations for them to be effective.
mappings in the context-cache or IOTLB. Any software
updates to the DMA-remapping structures (including
updates to not-present or erroneous entries) require
explicit invalidation.
(Sheet 3 of 4)
Description
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