CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 338

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

1.19.29
338
IOTLB_REG - IOTLB Invalidate Register
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
Register to invalidate IOTLB. The act of writing the upper byte of the IOTLB_REG with
IVT field set causes the hardware to perform the IOTLB invalidation.
Bit
63
Access
RW-SC
Default
Value
0b
Invalidate IOTLB (IVT)
Software requests IOTLB invalidation by setting this field.
Software must also set the requested invalidation
granularity by programming the IIRG field.
Hardware clears the IVT field to indicate the invalidation
request is complete. Hardware also indicates the
granularity at which the invalidation operation was
performed through the IAIG field. Software must not
submit another invalidation request through this register
while the IVT field is set, nor update the associated
Invalidate Address register.
Software must not submit IOTLB invalidation requests when
there is a context-cache invalidation request pending at this
DMA-remapping hardware unit.
Refer to Section 11 for software programming
requirements.
Hardware implementations reporting write-buffer flushing
requirement (RWBF=1 in Capability register) must
implicitly perform a write buffer flush before invalidating
the IOTLB.
Refer to Section 11.1 for write buffer flushing requirements.
0/0/0/DMIVC1REMAP
108-10Fh
0000000000000000h
RO; RW; RW-SC
64 bits
(Sheet 1 of 3)
Processor Configuration Registers
Description
Datasheet