CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 187

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

Processor Configuration Registers
1.13.40
Datasheet
LSTS - Link Status
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
Indicates PCI Express link status.
1:0
Bit
Bit
15
Access
Access
RWC
RW
Default
Default
Value
Value
00b
0b
Active State PM (ASPM)
Controls the level of active state power management
supported on the given link.
Note: “L0s Entry Enabled” indicates the Transmitter entering
L0s is supported. The Receiver must be capable of entering
L0s even when the field is disabled (00b).
ASPM L1 must be enabled by software in the Upstream
component on a Link prior to enabling ASPM L1 in the
Downstream component on that Link. When disabling ASPM
L1, software must disable ASPM L1 in the Downstream
component on a Link prior to disabling ASPM L1 in the
Upstream component on that Link. ASPM L1 must only be
enabled on the Downstream component if both components
on a Link support ASPM L1.
Link Autonomous Bandwidth Status (LABWS)
This bit is set to 1b by hardware to indicate that hardware has
autonomously changed link speed or width, without the port
transitioning through DL_Down status, for reasons other than
to attempt to correct unreliable link operation.
This bit must be set if the Physical Layer reports a speed or
width change was initiated by the downstream component
that was indicated as an autonomous change.
This bit must be set when the upstream component receives
eight consecutive TS1 or TS2 ordered sets with the
Autonomous Change bit set.
00:
01:
10:
11:
0/1/0/PCI
B2-B3h
1000h
RWC; RO
16 bits
(Sheet 3 of 3)
Disabled
L0s Entry Supported
L1 Entry Enabled
L0s and L1 Entry Supported
Description
Description
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