CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 125

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

Processor Configuration Registers
1.10.10
Datasheet
TERATE - Thermometer Mode Enable and Rate
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
This common register helps select between the analog and the thermometer mode and
also helps select the DAC settling timer.
Bit
7:4
Bit
0
Access
Access
RWC
RO
Default
Default
Value
Value
0h
0b
Reserved
Aux 0 Thermal Sensor Interrupt Event (A0TSIE)
0 = No trip for this event.
1 = An Aux0 Thermal Sensor trip event occurred based on a
Software must write a 1 to clear this status bit.
The following scenario is possible. An interrupt is initiated on
a rising temperature trip, the appropriate DMI cycles are
generated, and eventually the software services the
interrupt and sees a rising temperature trip as the cause in
the status bits for the interrupts.
0/0/0/MCHBAR
1070h
00h
RO; RW
8 bits
lower to higher temperature transition through the trip
point.
(Sheet 3 of 3)
Description
Description
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