CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 375

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

Processor Configuration Registers
1.20.21
Datasheet
IQA_REG - Invalidation Queue Address
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
Register to configure the base address and size of the invalidation queue. This register
is treated as RsvdZ by implementations reporting Queued Invalidation (QI) as not
supported in the Extended Capability register.
When supported, writing to this register causes the Invalidation Queue Head and
Invalidation Queue Tail registers to be reset to 0h.
63:12
11:3
2:0
Bit
Access
RO
RO
RO
00000000
Default
00000h
Value
000h
000b
Invalidation Queue Address (IQA)
This field points to the base of 4-KB aligned invalidation
request queue. Hardware ignores and not implement Bits
63:HAW, where HAW is the host address width.
Reads of this field return the value that was last
programmed to it.
Reserved
Queue Size (QS)
This field specifies the size of the invalidation request queue.
A value of X in this field indicates an invalidation request
queue of (X+1) 4-KB pages. The number of entries in the
invalidation queue is 2^^(X + 8).
0/2/0/GFXVTBAR
90-97h
0000000000000000h
RO
64 bits
Description
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