CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 160

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

1.13.12
1.13.13
160
IOBASE1 - I/O Base Address
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
This register controls the CPU to PCI Express-G I/O access routing based on the
following formula:
Only upper 4 bits are programmable. For the purpose of address decode address bits
A[11:0] are treated as 0. Thus the bottom of the defined I/O address range is aligned
to a 4-KB boundary.
IOLIMIT1 - I/O Limit Address
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
This register controls the CPU to PCI Express-G I/O access routing based on the
following formula:
Only upper 4 bits are programmable. For the purpose of address decode address bits
A[11:0] are assumed to be FFFh. Thus, the top of the defined I/O address range is at
the top of a 4-KB aligned address block.
IO_BASE=< address =<IO_LIMIT
IO_BASE=< address =<IO_LIMIT
7:4
3:0
7:4
3:0
Bit
Bit
Access
Access
RW
RO
RW
RO
Default
Value
Default
Value
0h
Fh
0h
0h
I/O Address Base (IOBASE)
Corresponds to A[15:12] of the I/O addresses passed by
bridge 1 to PCI Express-G.
BIOS must not set this register to 00h otherwise 0CF8h/
0CFCh accesses is forwarded to the PCI Express hierarchy
associated with this device.
Reserved
I/O Address Limit (IOLIMIT)
Corresponds to A[15:12] of the I/O address limit of Device
1. Devices between this upper limit and IOBASE1 is passed
to the PCI Express hierarchy associated with this device.
Reserved
0/1/0/PCI
1Ch
F0h
RO; RW
8 bits
0/1/0/PCI
1Dh
00h
RO; RW
8 bits
Description
Processor Configuration Registers
Description
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