CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 358

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

358
Bit
29
28
27
26
25
24
23
Access
RO
RO
RO
RO
RO
RO
RO
Default
Value
0b
0b
0b
0b
0b
0b
0b
Fault Log Status (FLS)
This field:
0 = Is cleared by hardware when software Sets the SFL field
1 = Is Set by hardware when hardware completes the set
Advanced Fault Logging Status (AFLS)
This field is valid only for implementations supporting
advanced fault logging. It indicates the advanced fault
logging status:
0 = Advanced Fault Logging is not enabled
1 = Advanced Fault Logging is enabled
Write Buffer Flush Status (WBFS)
This field is valid only for implementations requiring write
buffer flushing. This field indicates the status of the write
buffer flush command. It is:
0 = Cleared by hardware when hardware completes the
1 = Set by hardware when software sets the WBF field in
Queued Invalidation Enable Status (QIES)
This field indicates queued invalidation enable status.
0 = Queued invalidation is not enabled
1 = Queued invalidation is enabled
Interrupt Remapping Enable Status (IRES)
This field indicates the status of Interrupt-remapping
hardware.
0 = Interrupt-remapping hardware is not enabled
1 = Interrupt-remapping hardware is enabled
Interrupt Remapping Table Pointer Status (IRTPS)
This field indicates the status of the interrupt remapping
table pointer in hardware.
This field is cleared by hardware when software sets the
SIRTP field in the Global Command register.
This field is Set by hardware when hardware completes the
set interrupt remap table pointer operation using the value
provided in the Interrupt Remapping Table Address register.
Compatibility Format Interrupt Status (CIFS)
This field indicates the status of Compatibility format
interrupts on Intel®64 implementations supporting
interrupt-remapping. The value reported in this field is
applicable only when interrupt-remapping is enabled and
Legacy interrupt mode is active.
0 = Compatibility format interrupts are blocked.
1 = Compatibility format interrupts are processed as pass-
in the Global Command register.
fault-log pointer operation using the value provided in
the Advanced Fault Log register.
write buffer flushing operation.
the Global Command register.
through (bypassing interrupt remapping).
(Sheet 2 of 3)
Processor Configuration Registers
Description
Datasheet