CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 36

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

1.2.6.1
1.2.7
36
Table 1.
IOBAR Mapped Access to Device 2 MMIO Space
Device 2, integrated graphics device, contains an IOBAR register. If Device 2 is
enabled, then IGD registers or the GTT table can be accessed using this IOBAR. The
IOBAR is composed of an index register and a data register.
MMIO_Index: MMIO_INDEX is a 32-bit register. An IO write to this port loads the
offset of the MMIO register or offset into the GTT that needs to be accessed. An IO
Read returns the current value of this register. See IOBAR rules for detailed
information.
MMIO_Data: MMIO_DATA is a 32-bit register. An IO write to this port is re-directed to
the MMIO register pointed to by the MMIO-index register. An IO read to this port is re-
directed to the MMIO register pointed to by the MMIO-index register. See IOBAR rules
for detailed information.
The result of accesses through IOBAR can be:
Note GTT table space writes (GTTADR) are supported through this mapping
mechanism.
This mechanism to access internal graphics MMIO registers must not be used to access
VGA IO registers which are mapped through the MMIO space. VGA registers must be
accessed directly through the dedicated VGA IO ports.
System Management Mode (SMM)
The CPU handles all SMM mode transaction routing. The GMCH has no direct knowledge
of SMM mode. The GMCH will never allow IO devices access to CSEG/TSEG/HSEG
ranges. Refer to the CPU EAS for full register details, behaviors, and restrictions.
DMI Interface and PCI Express masters are not allowed to access the SMM space.
SMM Regions
Compatible (C)
TSEG (T)
1. Accesses directed to the GTT table. (i.e., route to DRAM)
2. Accesses to internal graphics registers with the GMCH (i.e. route to internal
3. Accesses to internal graphics display registers now located within the PCH. (i.e.,
SMM Space Enabled
configuration bus)
route to DMI).
(TOLUD-STOLEN-TSEG) to
TOLUD-STOLEN
000A_0000h to 000B_FFFFh
Transaction Address Space
Processor Configuration Registers
000A_0000h to 000B_FFFFh
(TOLUD-STOLEN-TSEG) to
TOLUD-STOLEN
DRAM Space (DRAM)
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