CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 198

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

1.13.46
198
LCTL2 - Link Control 2
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
15:13
Bit
12
11
10
Access
RW-S
RW-S
RW-S
RO
Default
Value
000b
0b
0b
0b
Reserved
Compliance De-emphasis (ComplianceDeemphasis)
This bit sets the de-emphasis level in Polling.Compliance
state if the entry occurred due to the Enter Compliance bit
being 1b.
Encodings:
1b -3.5 dB
0b -6 dB
When the Link is operating at 2.5 GT/s, the setting of this
bit has no effect. Components that support only 2.5 GT/s
speed are permitted to hardwire this bit to 0b. For a Multi-
Function device associated with an Upstream Port, the bit
in Function 0 is of type RWS, and only Function 0 controls
the component's Link behavior. In all other Functions of
that device, this bit is of type RsvdP. The default value of
this bit is 0b. This bit is intended for debug, compliance
testing purposes. System firmware and software is
allowed to modify this bit only during debug or compliance
testing.
Compliance SOS (compsos)
Ordered Sets periodically in between the (modified)
compliance patterns. For a Multi-Function device
associated with an Upstream Port, the bit in Function 0 is
of type RWS, and only Function 0 controls the
component's Link behavior. In all other Functions of that
device, this bit is of type RsvdP. The default value of this
bit is 0b. Components that support only the 2.5 GT/s
speed are permitted to hardwire this field to 0b.
Enter Modified Compliance (entermodcompliance)
When this bit is set to 1b, the device transmits modified
compliance pattern if the LTSSM enters
Polling.Compliance state. Components that support only
the 2.5GT/s speed are permitted to hardwire this bit to
0b. Default value of this field is 0b.
When set to 1b, the LTSSM is required to send SKP
0/1/0/PCI
D0-D1h
0002h
16 bits
RO; RW-S; RW
(Sheet 1 of 3)
Processor Configuration Registers
Description
Datasheet