CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 281

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

Processor Configuration Registers
1.18.17
Datasheet
PHMBASE_REG - Protected High-Memory Base Register
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
Register to setup the base address of DMA protected high-memory region. This register
must be setup before enabling protected memory through PMEN_REG, and must not be
updated when protected memory regions are enabled.
When LT.CMD.LOCK.PMRC command is invoked, this register is locked (treated RO).
When LT.CMD.UNLOCK.PMRC command is invoked, this register is unlocked (treated
RW).
This register is always treated as RO for implementations not supporting protected high
memory region (PHMR field reported as 0 in the Capability register). The alignment of
the protected high memory region base depends on the number of reserved bits (N) of
this register. Software may determine the value of N by writing all 1's to this register,
and finding most significant zero bit position below host address width (HAW) in the
value read back from the register. Bits N:0 of the limit register is decoded by hardware
as all 0’s.
63:21
20:0
Bit
Access
RW
RO
00000000
000000h
Default
Value
000h
Protected High-Memory Base (PHMB)
This register specifies the base of size aligned, protected
memory region in system memory. Hardware may not utilize
Bits 63:HAW, where HAW is the host address width. The
protected high-memory region has a minimum size of 2 MB
and must be size aligned.
Reserved
0/0/0/VC0PREMAP
70-77h
0000000000000000h
RO; RW
64 bits
Description
281