CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 260

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

260
Bit
4
3
2
1
0
Access
RO
RO
RO
RO
RO
Default
Value
0b
0b
0b
0b
0b
Extended Interrupt Mode (EIM)
0 = Hardware supports only 8-bit APICIDs (Legacy
1 = Hardware supports Extended Interrupt Mode (32-bit
Interrupt Remapping Support (IR)
0 = Hardware does not support interrupt remapping.
1 = Hardware supports interrupt remapping.
Device IOTLB Support (DI)
0 = Hardware does not support device- IOTLBs.
1 = Hardware supports Device-IOTLBs.
Queued Invalidation Support (QI)
0 = Hardware does not support queued invalidations.
1 = Hardware supports queued invalidations.
Coherency (C)
0 = Indicates that hardware accesses to the root, context,
1 = Indicates that hardware accesses to the root, context,
Hardware writes to the advanced fault log is required to be
coherent.
Implementations reporting this field as Set must also
support Queued Invalidation (QI = 1b).
Implementations reporting this field as Set must also
support Queued Invalidation (QI = 1b).
Interrupt Mode) on Intel® 64 and IA-32 platforms and
16- bit APIC-IDs on Itanium® platforms.
APIC-IDs) on Intel® 64 platforms. This field is valid
only when the IR field is reported as Set.
and page table structures are non-coherent (non-
snoop).
and page table structures are coherent (snoop).
(Sheet 3 of 3)
Processor Configuration Registers
Description
Datasheet