CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 242

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

1.16.24
1.16.25
1.16.26
242
SSRW - Software Scratch Read Write
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
BSM - Base of Stolen Memory
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
Graphics Stolen Memory and TSEG are within DRAM space defined under TOLUD. From
the top of low used DRAM, processor claims 1 to 64 MBs of DRAM for internal graphics
if enabled.
The base of stolen memory will always be below 4G. This is required to prevent aliasing
between stolen range and the reclaim region.
HSRW - Hardware Scratch Read Write
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
31:20
31:0
15:0
19:0
Bit
Bit
Bit
Access
Access
Access
RW
RW
RO
RO
00000000h
Default
Default
Value
00000h
Default
Value
000h
Value
0000h
Base of Stolen Memory (BSM)
This register contains Bits 31:20 of the base address of stolen
DRAM memory. The host interface determines the base of
Graphics Stolen memory by subtracting the graphics stolen
memory size from TOLUD. See Device 0 TOLUD for more
explanation.
Reserved
FLR, Core
FLR, Core
RST/
PWR
RST/
PWR
0/2/0/PCI
58-5Bh
00000000h
RW
32 bits
0/2/0/PCI
5C-5Fh
00000000h
RO
32 bits
0/2/0/PCI
60-61h
0000h
RW
16 bits
Reserved
Reserved
Description
Processor Configuration Registers
Description
Description
Datasheet