CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 289

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

Processor Configuration Registers
Datasheet
5:0
Bit
6
Access
W
W
Default
Value
00h
0h
Invalidation Hint (IH)
The field provides hint to hardware to preserve or flush the
non-leaf (page-directory) entries that may be cached in
hardware.
0 = Software may have modified both leaf and non-leaf
On a pages elective invalidation request, hardware must
flush both the cached leaf and non-leaf page-table Value
returned on read of this field is undefined. Entries
corresponding to mappings specified by ADDR and AM fields.
1 = Software has not modified any non-leaf page-table
The value in this field specifies the number of low order bits
of the ADDR field that must be masked for the invalidation
operation. Mask field enables software to request
invalidation of contiguous mappings for size-aligned
regions.
For example: Mask Value ADDR bits masked Pages
invalidated:
Hardware implementations report the maximum supported
mask value through the Capability register.
Value returned on read of this field is undefined.
Address Mask (AM)
Value
Mask
page-table entries corresponding to mappings specified
in the ADDR and AM fields.
entries corresponding to mappings specified in the
ADDR and AM fields. On a page-selective invalidation
request, hardware may preserve the cached non-leaf
page-table entries corresponding to mappings specified
by ADDR and AM fields.
(Sheet 2 of 2)
0
1
2
3
4
5
6
7
8
ADDR
13:12
14:12
15:12
16:12
17:12
18:12
19:12
None
Bits
12
Description
Invalidated
Pages
128
256
512
16
32
64
1
2
8
289