CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 52

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

1.8.5
52
RID - Revision Identification
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
This register contains the revision number of the processor. The Revision ID (RID) is a
traditional 8-bit Read Only (RO) register located at offset 08h in the standard PCI
header of every PCI/PCI Express compatible device and function.
Following reset, the SRID is returned when the RID is read at offset 08h. The SRID
value reflects the actual product stepping. To select the CRID value, BIOS/configuration
software writes a key value of 69h to Bus 0, Device 0, Function 0 (DMI device) of the
CPU’s RID register at offset 08h. This causes the CRID to be returned when the RID is
read at offset 08h.
Stepping Revision ID (SRID)
This register contains the revision number of the CPU.
The SRID is a 8-bit hardwired value assigned by Intel, based on product’s stepping. The
SRID is not a directly addressable PCI register. The SRID value is reflected through the
RID register when appropriately addressed.
2:0
Bit
7
6
5
4
3
Access
RO
RO
RO
RO
RO
RO
Default
Value
000b
1b
0b
0b
1b
0b
Fast Back-to-Back (FB2B)
This bit is hard wired to 1. Writes to these bit positions
have no effect. Device 0 does not physically connect to
PCI_A. This bit is set to 1 (indicating fast back-to-back
capability) so that the optimum setting for PCI_A is not
limited by the processor.
Reserved
66-MHz Capable (66MC)
Does not apply to PCI Express. Must be hard wired to 0.
Capability List (CLIST)
This bit is hard wired to 1 to indicate to the configuration
software that this device/function implements a list of new
capabilities. A list of new capabilities is accessed via
register CAPPTR at configuration address offset 34h.
Register CAPPTR contains an offset pointing to the start
address within configuration space of this device where the
Capability Identification register resides.
Reserved
Reserved
0/0/0/PCI
8h
12h
RO
8 bits
(Sheet 2 of 2)
Processor Configuration Registers
Description
Datasheet