CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 47

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CP80617004119AES LBU3

Manufacturer Part Number
CP80617004119AES LBU3
Description
Manufacturer
Intel
Datasheet

Specifications of CP80617004119AES LBU3

Lead Free Status / RoHS Status
Compliant
Processor Configuration Registers
Datasheet
Vendor Identification
Device Identification
PCI Command
PCI Status
Revision Identification
Class Code
Master Latency Timer
Header Type
Subsystem Vendor Identification
Subsystem Identification
Capabilities Pointer
PCI Express Egress Port Base
Address
Processor Memory Mapped
Register Range Base
Processor Graphics Control
Register
Device Enable
Root Complex Register Range
Base Address
Legacy Access Control
Remap Base Address Register
Remap Limit Address Register
Top of Memory
Top of Upper Usable DRAM
Graphics Base of Stolen Memory
Base of GTT stolen Memory
TSEG Memory Base
Top of Low Usable DRAM
Primary Buffer Flush Control
Secondary Buffer Flush Control
Error Status
Error Command
SMI Command
Table 3.
Register Name
Device 0 Function 0 Register Summary (Sheet 1 of 2)
VID
DID
PCICMD
PCISTS
RID
CC
MLT
HDR
SVID
SID
CAPPTR
PXPEPBAR
MCHBAR
GGC
DEVEN
DMIBAR
LAC
REMAPBASE
REMAPLIMIT
TOM
TOUUD
GBSM
BGSM
TSEGMB
TOLUD
PBFC
SBFC
ERRSTS
ERRCMD
SMICMD
Register
Symbol
Register
Start
AC
CA
CC
2C
2E
34
40
48
52
54
68
97
98
9A
A0
A2
A4
A8
B0
C0
C4
C8
D
0
2
4
6
8
9
E
Register
End
CD
2D
A1
AB
C9
C8
2F
34
47
4F
53
57
6F
97
99
9B
A3
A7
AF
B1
C3
C7
D
1
3
5
7
8
B
E
8086h
0044h
0006h
0090h
12h
060000h
00h
00h
0000h
0000h
E0h
00000000000
00000h
00000000000
00000h
0030h
0000210Bh
00000000000
00000h
00h
03FFh
0000h
0001h
0000h
00000000h
00000000h
00000000h
0010h
00000000h
00000000h
0000h
0000h
0000h
Default
Value
RO
RO
RO; RW
RWC; RO
RO
RO
RO
RO
RW-O
RW-O
RO
RW-L; RO
RW-L; RO
RW-L; RO
RW
RW-L; RO
RW
RO; RW-L
RW-L; RO
RW-L; RO
RO; RW-L
RW-L; RO
RO; W
RO; RWC-S
RO; RW
RO; RW
RW-L; RO;
RO; RW-L
RO; RW-L
RW-L
RO; W
Access
47

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